Semiconductor integrated circuits (ICs) are produced by a plurality of processes in a wafer fabrication facility (fab). These processes, and associated fabrication tools, may include thermal oxidation, diffusion, ion implantation, rapid thermal processing (RTP), chemical vapor deposition (CVD), physical vapor deposition (PVD), epitaxy, photolithography and etching.
In photolithography, light transfers a geometric pattern from a photo mask to a light-sensitive chemical photoresist on the substrate. The mask is created using a layout generated by an electronic design automation (EDA) tool. The EDA tool convert's a designer's gate level hardware design to a transistor level layout of geometric patterns on a plurality of layers. Each layer may be patterned by one or more masks.
At the smaller feature sizes of advanced technologies, diffraction effects become significant. The conventional diffraction-limited resolution is given by the Rayleigh criterion as 0.61λ/NA, where NA is the numerical aperture and λ is the wavelength of the illumination source. When the feature dimensions are below this size, diffraction causes rounding of corners and line-width differences between isolated pattern (“iso”) and dense pattern regions. EDA tools apply optical proximity correction (OPC) to compensate for these diffraction effects. OPC may adjust the layout patterns by moving edges or adding extra polygons to the pattern written on the photomask. To keep run time at a reasonable length, OPC may be implemented using pre-computed look-up tables based on width and spacing between features.
Because of the nature of diffraction effects, a pattern in a dense region benefits less from a given OPC modification than the same pattern benefits from the same correction when located in an iso region. Thus, an EDA tool may configure dense and iso patterns on a photomask differently, in order to achieve the same line width in the final dense and iso patterns formed on the substrate.